A clock tree is used to distribute a clock to endpoints (e.g., flip-flops) in a synchronous digital integrated circuit (IC), such as a microprocessor. A synchronous design typically requires that all endpoints be clocked at the same time, or that their clocks have known offsets relative to each other. Failure to achieve required arrival times of clocks at endpoints results in either degraded performance (longer cycle time) or outright failure (a race condition).
It is a difficult challenge to design a clock distribution network that ensures synchronicity of clock arrival times, typically requiring special purpose software. However, the special purpose software may use various design assumptions and algorithms based off of a default specification file of the software tool (“tool specification”) that may produce unsatisfactory results. Accordingly, a clock network designer may be required to manually input and change one or more design parameters in the tool specification file in an attempt to achieve the desired clock arrival times of a clock network. However, achieving the proper result may entail many different iterations of changing one or more input design parameters in the software tool, generating a clock network with the software tool based on the design parameters, and determining whether the generated clock network satisfies the design constraints. This manual process of trial and error can be tedious and time consuming.